TSMC’s first virtual tech symposium showcased the release of a number of videos and updates on its manufacturing technology. Over the past few years, TSMC has pulled even with Intel, then taken a leadership position in semiconductors. After Intel announced a 7nm delay for its CPUs earlier this year, TSMC is seizing an opportunity to make its own mark as the leader of the industry.
According to Y.J. Mii, senior VP of TSMC, the company has a plan for continuing to offer meaningful node improvements down to N3 and below, though only density will scale at anything like historic levels. We’ll discuss the implications of this below.
First, a broad overview of TSMC’s product mix. The company did not state if “CPU/GPU” includes products from companies like Apple, or if those sections refer AMD’s 7nm businesses. If we assume the former, Apple and other ARM devices would account for the 2018 “CPU/GPU” volume, with AMD presumably stepping into that group as well with the launch of the Ryzen 3000 family and RDNA-based GPUs back in 2019. Since the 2020 graph-to-date presumably doesn’t include much input from Nvidia, we might see these numbers shift further once Ampere is included — or TSMC might have estimated the GPU’s expected contribution to 7nm design wins.
The overall point is that 7nm is supported by a range of product families, not just a single chip type or category, and it contributed 36 percent of TSMC’s Q2 2020 revenue. It would be interesting to know if the surge of interest in topics like AI and machine learning have increased the absolute pool of 7nm customers. Back when GlobalFoundries canceled its own leading-edge deployment, the stated reason was a lack of expected customers for the node. There’s a lot of startup activity focused on AI and ML, but some of these projects use older nodes or might be expected to produce very limited volumes.
Next, some updates on N5 and N6. According to TSMC, N6 offers a 1.18x logic density improvement over N5, but no other gains are cited. For the N5 node (as compared with N7), the gains are larger: 1.15x performance, or 1.3x improved power consumption, or a 1.8x improved logic density. N5P is expected to deliver a further 1.05x performance or a 1.1x power reduction compared with N5.
N4, which TSMC is disclosing today, will reduce mask layer requirements and offers a straightforward migration path. Mii did not provide additional details on what improvements N4 offers, or which specific customers would migrate to the node. Risk production is expected in Q4 2021, with volume production planned in 2022.
As for N3, TSMC expects it to be the newest and most-advanced node available in 2022. Gains over N5 are similarly small, with an improvement of just 1.1 – 1.15x in performance and 1.25x – 1.3x in power consumption. These gains are relative to N5, not N5P. Compared with 7nm, N3 should offer 1.25x – 1.35x improved performance at the same power or 1.55x – 1.6x reduced power consumption at the same performance. Keep in mind that all of the multiples you see tossed around during these comparisons assume a hypothetical idealized transistor that doesn’t necessarily conform to what AMD, Nvidia, or even Intel might actually build. Manufacturers typically don’t optimize for any single category but take advantage of some of the improvements offered in all three.
One reason TSMC may have moved to these subdivided nodes, with multiple relatively similar options available, is to offer customers the option to make small iterative improvements and launch new products without needing to rebuild them according to new design rules. Some of you may remember that TSMC introduced so-called “half nodes” years ago, to offer iterative steps for foundry customers that wanted to take advantage of smaller improvements more quickly. The half-node nomenclature isn’t used any longer, but that seems to be the conceptual underpinning of this idea. If you build a 5nm CPU and don’t want to build a new part for 3nm, you can migrate to 5NP or possibly N4, achieve some improvements on cost and density, and spread the cost of the new node shift over several years.
N3 will continue to use FinFETs rather than transitioning to GAA (Gate-All-Around) FETs. That’s different from Samsung, which has signaled its intention to use GAA at the 3nm node. Samsung seems to have had some problems with its own 7nm ramp, however, so it’s possible these plans could change.
TSMC continues to work on nanosheets and nanowires and has demonstrated a 32Mb nanosheet SRAM that remained operable at 0.46v. The stacked “sheets” in the image above show the transition from a FinFET-based approach, though TSMC has no plans to commercialize this technology through 2022.
TSMC also discussed some specific technological achievements it has made, though not all of them were linked to deployment on a particular node. It has successfully deployed a carbon nanotube power-gating device in back end of line (BEOL) 28nm CMOS and successfully demonstrated an air spacer to reduce gate-to-drain capacitance by 10 percent. It also has a roadmap for delivering better via resistance and circuit RC delay.
Some of these individual improvements come with impressive gains, like a claimed 50 percent reduction in via resistance, but I’m assuming that these specific, called-out advances are some of the means by which TSMC will deliver the performance, power consumption, and density improvements it has promised for future nodes. They aren’t bonuses expected to move the needle further — they’re the means by which we’re going to be able to move it at all.
The characteristics TSMC has given for its upcoming nodes will have a meaningful impact on the types of chips AMD, Nvidia, Qualcomm, and Apple bring to market through 2023 – 2024 given the lag between when TSMC enters high volume manufacturing and when companies launch products.
What TSMC is signaling, in aggregate, is that we can expect meaningfully better power consumption and transistor densities, but performance at the per-transistor level is only going to improve modestly. The performance improvement from TSMC’s 16FF to its 7nm node will not be replicated from N7 to N3. This doesn’t mean silicon designers won’t find ways to improve performance — it just means they may have to do so through further efficiency improvements in how they use transistors or the types of chips they design. A recent study suggested manufacturers have often struggled to achieve these improvements, relying instead on the gains each successive manufacturing node could deliver. With strong density gains generation-on-generation but smaller improvements to power and performance, expect to see more firms moving to advanced packaging and disaggregation, hoping to gain additional wiggle room through higher efficiencies.
All images, including feature image, courtesy of TSMC
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